Design of 4-bit flash ADC

Abstract

This project presents design of low power comparator and low power encoder for 4 bit flash ADC. A 4 bit Flash ADC required 15 comparators and a thermometer code to binary code encoder. The major issue in the design of Flash ADC is the large power consumption due to the large number of comparators used. So in order to reduce the power consumption of Flash ADC, we have to design a comparator with very low power consumption. Different comparators are designed and their power consumptions are observed. The comparator with lowest power consumption is selected. Encoder is design with XOR gate. Both comparator and encoder are designed and simulated in CMOS 90nm technology. The schematic of the all circuits are design with LtSpice and DSCH3. Microwind software is used to design the layout. These designs have been also tested in CMOS 65nm and 45nm technology. Comparators and encoder have better stability and power consumption is less.