Low power high speed operational amplifier design using cadence

Abstract

This paper presents a new approach to design 0f low power high speed operational Amplifier. The amplifying cell consist of two parts, differential amplifier and common source Amplifier. We are design a two stage CMOS operational amplifier which operate at 1.8Vpower supply and whose input is dependent on bias current. The supply voltage has been scaled down in order to reduced the overall power consumption of the system. The main aim of our work is to increase the slew rate of the op-amp without decreasing the gain of the amplifier. At large supply voltage, there is a trade-off among speed, power, GBW and gain but this op-amp has very low power consumption with a high driving capacity. The op-amp provide a gain pf 60dB and bandwidth of 30Mhz and 2pf load capacitor and output slew rate is 20V/μs. Keywords:-Slew rate, GBW, PM, gain and bandwidth.